Ultra-low-power SoCs for battery-powered endpoint IoT devices

September 14, 2020 //By Rich Pell
Ultra-low-power SoCs for battery-powered endpoint IoT devices
Ultra-low-power mixed-signal semiconductor company Ambiq has introduced a new SoC family for battery-powered, intelligent endpoint IoT devices featuring always-on voice-processing.

The Apollo4 SoC family is a fourth-generation system processor solution built upon the company's proprietary Subthreshold Power-Optimized Technology (SPOT) platform. The Apollo4's complete hardware and software solution, says the company, enables the battery-powered endpoint devices of tomorrow to achieve a higher level of intelligence without sacrificing battery life.

The Apollo4 is designed to enable manufacturers to create leading-edge endpoint devices leveraging the company's SPOT platform with its easy-to-use, rich peripheral set. The Apollo4, says the company, is purpose-built to serve as both an application processor and a coprocessor for battery-powered endpoint devices, including smartwatches, children's watches, fitness bands, animal trackers, far-field voice remotes, predictive health and maintenance devices, smart security devices, and smart home devices.

"As the market is shifting towards adding billions of smart devices at endpoints in the coming years," says Dan Cermak, VP of Architecture and Product Planning at Ambiq, "the need for energy efficiency is beyond critical to sustaining the realization of an IoT world where everything stays connected 24/7. Building on the advanced technologies from Arm and TSMC, our Apollo4 SoC family presents the perfect combination of increased system capability with significantly reduced power consumption for all battery-powered endpoint devices."

Implemented on a TSMC 22-nm ULL process and based on a 32-bit Arm Cortex-M4 processor with FPU and Arm Artisan physical IP, the Apollo4 achieves 3 µA/MHz from MRAM with low deep sleep current modes and up to 192 MHz clock frequency using TurboSPOT. Other features include a 2D/2.5D graphics accelerator and MIPI DSI 1.2 with up to two lanes at 500Mbps per lane, eight PDM channels, two stereo I2S channels with ASRC, and an ultra-low power ADC for analog microphones.

With up to 2MB of MRAM and 1.8MB of SRAM, the Apollo4, says the company, has enough compute and storage to handle complex algorithms and neural networks while displaying vibrant, crystal-clear, and smooth graphics. If additional memory is required, external memory is supported through


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.