SoC emulation system offers 'breakthrough' 10 MHz performance

May 17, 2021 // By Rich Pell
SoC emulation system offers 'breakthrough' 10 MHz performance
Electronic design automation company Synopsys has announced its next-generation verification hardware solution enabling 10 MHz performance, power-aware emulation, and system-level debug.

The ZeBu EP1 emulation system delivers 10-MHz performance to speed hardware and software verification of complex system-on-chip (SoC) designs of up to 2 billion gates in areas such as high-performance computing (HPC), 5G, GPU, artificial intelligence (AI) and automotive. The system, says the company, leverages its proven direct-connect architecture to optimize design communication and deliver unprecedented emulation performance.

In addition, the unique power-aware emulation, system-level debug, hybrid emulation and virtual host and device capabilities in ZeBu are designed to accelerate SoC product readiness across both hardware and software domains.

"We continue to accelerate innovation for our verification hardware by collaborating with industry-leading customers," says Manoj Gandhi, general manager of the Verification Group at Synopsys. "ZeBu EP1 represents the convergence of multiple hardware and software technologies to deliver breakthrough performance and debug. The unique fast emulation capability in ZeBu is enabling electronics companies to develop and verify the most advanced SoCs with full software stacks."

Recent innovations in the ZeBu family of hardware acceleration and FPGA-based hardware emulation products include:

  • ZeBu EP1, the industry's first 10 MHz emulation system, utilizing Synopsys' proven direct-connect architecture, optimizes design communication to accelerate hardware and software verification for SoC designs of up to 2 billion gates.
  • ZeBu Empower emulation system, the industry's first SoC power-aware emulation system, enabling multiple iterations per day with actionable power profiling in the context of the full design and its software workload.
  • ZeBu System Level Debug , the proven approach to efficiently debug complex SoC with billion-cycle software workloads, leveraging high-bandwidth host interface for continuous data streaming and deterministic replay for eliminating redundant emulation runs.
  • ZeBu Hybrid Emulation with Virtualizer virtual prototyping, supported by an extensive library of virtual processor, memory and interface models, delivers 70-100x throughput gain for OS boot enabling more complex software validation and earlier tape-out.
  • ZeBu Virtual Host and Device models for PCIe 5.0, USB3, SATA, Ethernet, and NVMe enable validation of host to device software

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