The family is pin compatible with its GD32 ARM-based microcontrollers but thas dynamic power consumption 50 percent and the standby power consumption 25 percent lower than the GD32 ARM Cortex-M3 device.
The GD32V, which GigaDevice says is the first RISC-V microcontroller. is based around the Bumblebee RISC-V core developed by GigaDevice and processor core IP developer Nuclei System Technology. The core has a two-stage variable-length pipeline microarchitecture with a streamlined dynamic branch predictor and instruction prefetch unit, while it incorporates a variety of low-power design methods including a single-cycle hardware multiplier, hardware divider and acceleration unit and a power management unit that supports two-levels of sleep mode. There is a 64bit timer and can generate timer interrupts defined by the RISC-V standard.
"GigaDevice is the first in the industry to launch 32bit general-purpose MCU products based on RISC-V architecture and continues to build and strengthen the RISC-V development ecosystem," said Deng Yu, executive VP of GigaDevice, general manager of GigaDevice MCU business unit. "
The chip is powered by 2.6V-3.6V and the I/O ports can withstand 5V voltage level. It is equipped with a 16-bit advanced timer supporting three-phase PWM complementary outputs and Hall acquisition interface for vector control. Also, it has up to four 16-bit general-purpose timers, two 16-bit basic timers, and two multi-channel DMA controllers. The interrupt controller (ECLIC) provides up to 68 external interrupts and can be nested with 16 programmable priority levels to enhance the real-time performance of high-performance control.
In benchmarks the chip produces 153DMIPS at 108MHz with 360 CoreMark points, 15 percent higher than the M3. The family supports 16KB to 128KB of on-chip flash and 6KB to 32KB of SRAM cache, as well as GigaDevice's patented gFlash technology that allows high-speed core accesses to flash in zero wait time to further reduce the power consumption.