New FPGAs optimized for AI/ML, high-bandwidth networking

May 22, 2019 //By Rich Pell
New FPGAs optimized for AI/ML, high-bandwidth networking
Achronix Semiconductor (Santa Clara, CA) has introduced a new FPGA family specifically designed to meet the growing demands of artificial intelligence/machine learning (AI/ML) and high-bandwidth data acceleration applications.

Based on a new, highly optimized architecture, the Achronix Speedster7t FPGA family, says the company, goes beyond traditional FPGA solutions by featuring ASIC-like performance, FPGA adaptability, and enhanced functionality to streamline design. The devices feature a new 2D network-on-chip (NoC), and a high-density array of new machine learning processors (MLP).

By blending FPGA programmability with ASIC routing structures and compute engines, says the company, the Speedster7t family creates a new "FPGA+" class of technology that can address the rapidly evolving use cases of AI/ML.

"We are at the beginning of a high-growth phase of intelligent, self-learning computation that will have broad impacts on all aspects of our daily lives," says Robert Blake, President and CEO of Achronix Semiconductor. "The Speedster7t family is the most exciting announcement in the history of Achronix. The Speedster7t family is the fusion of flexible FPGA technology with ASIC core efficiency to deliver a new "FPGA+" class of chips that truly push the boundaries of high-performance compute acceleration."

In developing the Speedster7t FPGAs, the company redesigned the entire FPGA architecture to balance on-chip processing, interconnect and external I/O, to maximize the throughput of data-intensive workloads such as those found in edge- and server-based AI/ML applications, networking, and storage. Speedster7t devices are manufactured on TSMC's 7nm FinFET process and are designed to accept massive amounts of data from multiple high-speed sources, distribute that data to programmable on-chip algorithmic and processing units, and then deliver those results with the lowest possible latency.

Speedster7t devices include high-bandwidth GDDR6 interfaces, 400G Ethernet ports, and PCI Express Gen5 - all interconnected to deliver ASIC-level bandwidth while retaining the full programmability of FPGAs, says the company. The devices range from 363K to 2.6M six-input LUTs.

The ACE design tools that support all of the company's products are available today. The first Speedster7t devices and development boards will be available in Q4 2019.

Achronix Semiconductor

Related articles:
Achronix moves FPGA cores to 7nm,


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