Neural processor unit IP for more efficient AI solutions

August 15, 2019 //By Rich Pell
Neural processor unit IP offers more efficient AI solutions
Silicon-platform-as-a-service (SiPaaS) company VeriSilicon (San Jose, CA) has announced a highly scalable and programmable processor for computer vision and artificial intelligence.

The VIP9000 adopts Vivante Corporation's latest VIP V8 neural processing unit (NPU) architecture and the Tensor Processing Fabric technology to deliver what is claimed to be neural network inference performance with industry-leading power efficiency (TOPS/W) and area efficiency (mm 2/W). The device features scalable compute capability ranging from 0.5 TOPS (Tera-Operations-Per-Second) to 100s of TOPS.

"Neural Network technology is continuing to grow and evolve and there are so many applications across the board when it comes to computer vision, pixel processing for super resolution, and audio and voice processing," says Wei-Jin Dai, VeriSilicon's Executive Vice President and GM of Intellectual Property Division. "In just a few short years, more than 25 unique licensees have adopted VIP technology across a wide range of applications, from wearable and IoT devices, IP cameras, surveillance cameras, smart home and appliances, mobile phones, laptops, to automotive (ADAS, autonomous driving) and edge servers, which is a true testament to the demand of the products and technology."

Industries that will benefit from the VIP9000, says the company, include AI vision, AI voice, AI pixel, or Artificial Intelligence of Things (AIOT) applications. For smart home and AIOT applications, VIP9000 offers several highly optimized, high precision recognition engines.

The latest release contains the following new features:

  • A more flexible data distributor and processing core configurator: Brings high MAC utilization to a wide range of filter shapes and sizes in modern neural network models;
  • New data format support for Bfloat16: On top of existing INT8, INT16, and Float16 support, Bfloat16 delivers better accuracy for AI training;
  • FLEXA API support: A hardware and software protocol that enables efficient data communication between multiple pixel processing IP blocks. Systems using VeriSilicon's IPS, Video CODEC, NPU, or 3rd party IP compliant with FLEXA API can run AI applications with reduced DDR traffics and low pixel processing latency for applications running thru multiple IPS;
  • Task-specific engines designed for speeding up commonly used AI applications:

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