Developed first by semiconductor foundry TSMC in 2012, CoWoS packaging, says the company, is critical to successful deployment of today's high-performance computing ASICs. The 2.5D wafer-level multi-chip packaging technology incorporates multiple side-by-side die on a silicon interposer, with individual chips bonded through micro-bumps on a silicon interposer forming a chip-on-wafer.
Packaging is completed by bonding a package substrate. The configuration, says the company, improves interconnect density and performance.
"Packaging is the new 'Moore's Law' for powerful high-performance computing challenges," says Alchip Technologies' President and CEO, Johnny Shen. "Understanding and applying the technology is critical to meeting the demand for more functionality and greater performance in a smaller physical footprint. Our leading edge CoWoS service platform is scoped to cover from system planning, interposer design, test, qualification, and to production."
Today's CoWoS chiplet sets, says the company, include high-performance system-on-chip (SoC) and a high-performance memory (HBM) block. The CoWoS service covers multiple package designs. A new SoC and HBM2E high-bandwidth memory configuration in a 65 mm x 65 mm footprint joins an earlier SoC and HBM2E 55 mm x 55 mm footprint. Alchip supports all TSMC 2.5D packaging solutions.
The company's CoWoS design service covers system planning that includes architecture planning, power supply planning, package ball assignments, interposer die placement, SoC floor planning, and IP/IO placement collaboration. It also includes full-service interposer physical design, substrate design, design-for-test (DFT) logic insertion, logic verification among interposer, SoC, and package, and CoWoS/package mechanical and warpage simulation.
CoWoS, says the company, is ideal for hyperscalers, OEMs, and fabless IC device companies who require product-specific, high performance ICs.