Blockchain FPGA frameworks overcome 'impossible triangle'

March 15, 2019 //By Rich Pell
Blockchain FPGA frameworks overcome 'impossible triangle'
San Francisco-based startup Accelor has emerged from stealth claiming to be the first hardware accelerator bridging the blockchain and cloud industries.

In its announcement, the company unveiled customized hardware designed to "unshackle" blockchain applications from the constraints of legacy cloud infrastructure. Its field programmable gate array (FPGA) frameworks are designed to optimize computing performance and decentralized security.

The company's first two products (Accelor Performance Engine (APE) and Accelor Security Architecture (ASA)) provide the underlying hardware designed to effectively overcome the tradeoffs between security, performance, and decentralization - blockchain's so-called "impossible triangle."

"Blockchain has introduced valuable new techniques for how we share and secure private data, but the industry's software has run up against an impossible triangle between decentralization, security, and performance," says GJ Chu, Co-founder, Accelor. "Blockchain applications currently operate on top of retrofitted legacy hardware that relies on a 'security by patch' process and is unsuited to the rigorous computation demanded by decentralized protocols.

"Commodity CPUs are not friendly to the cryptographic, network, and database operations necessary for these systems to scale without sacrificing security and it is paramount for the industry to move these intensive computing functions onto dedicated hardware," says Chu. "We are excited to release a crucial part of the data center infrastructure that will help Blockchain deliver on its enormous potential."

Accelor Performance Engine overcomes barriers to scalability, says the company, by providing dedicated hardware infrastructure to optimize the computation of intensive cryptography, storage of distributed ledger data, and transaction relays over networks. APE has been tested using Hyperledger Fabric in a live real-world environment to sustain 10x greater end-to-end throughput against software-only implementations, and has a theoretical limit upwards of 200,000 transactions per second (TPS).

Accelor Security Architecture is designed to remove the most harmful threats endemic to CPU-based networking. Threats such as Spectre, Meltdown, and Foreshadow have been reported as critical in all the latest Trusted Execution Environments (TEE) of commercial processors, and enable malicious actors to read the most sensitive information, such as private cryptographic keys, which is detrimental to the development of


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