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Report: IBM plans US$730 million Canadian chip expansion
Report: IBM plans US$730 million Canadian chip expansion
Business news |
IBM Corp. plans to spend CA$1 billion (about US$730 million) upgrading and expanding its assembly, testing and packaging (ATP) facility…
Chiplet startup Eliyan now backed by all major memory firms
Chiplet startup Eliyan now backed by all major memory firms
Business news |
Chiplet interconnect startup Eliyan Corp. (Santa Clara, Calif.) has raised US$60 million in a Series B funding round led by…
Scalable sub-pJ/bit chiplet interconnect with 10m reach
Scalable sub-pJ/bit chiplet interconnect with 10m reach
Technology News |
Avicena is announcing its new scalable LightBundle chiplet interconnect at OFC 2024 in San Diego, CA. The chiplet interconnect extends…
Silicon Box adds detail to its Italian job
Silicon Box adds detail to its Italian job
News |
Silicon Box has confirmed it plans to collaborate with the Italian government and invest up to €3.2 billion (about US$3.5…

Silicon Box to build €3.2 billion Italian chiplet factory
Silicon Box to build €3.2 billion Italian chiplet factory
Business news |
Singapore startup Silicon Box Pte. Ltd. will spend €3.2 billion (about US$3.5 billion) building a chiplet packaging factory in northern Italy, newswires quote Industry Minister Adolfo Urso saying Monday morning.
Socionext collaborates with Arm and TSMC on 2nm chiplet development
Socionext collaborates with Arm and TSMC on 2nm chiplet development
Business news |
Next-generation compute chiplet-based proof-of-poncept leverages Arm Neoverse CSS technology and TSMC silicon process Along with advanced packaging.
QuickLogic, YorChip to develop FPGA chiplets
QuickLogic, YorChip to develop FPGA chiplets
Business news |
FPGA vendor QuickLogic Corp. has partnered with YorChip Inc. (San Ramon, Calif.) to create UCIe-compatible FPGA chiplets. UCIe stands for Universal Chiplet Interconnect Express. It is an open specification for…
TSMC grabs land for another back-end packaging fab
TSMC grabs land for another back-end packaging fab
Business news |
Leading chip foundry TSMC is planning to spend NT$90 billion (about US$2.9 billion) on an advanced packaging facility in Tongluo Science Park, Miaoli County, Taiwan. This will be TSMC’s second…
TSMC’s biggest chiplet backend fab opens for business
TSMC’s biggest chiplet backend fab opens for business
Business news |
TSMC has opened its Advanced Backend Fab 6 – a major packaging and testing fab to realize 3DFabric integration, the foundry’s approach to chiplet and multi-die component assembly. The fab…
Eliyan gets 40Gbps/bump chiplets back from TSMC
Eliyan gets 40Gbps/bump chiplets back from TSMC
Technology News |
Chiplet startup Eliyan Corp. (Santa Clara, Calif.) has received its first silicon in 5nm manufacturing process technology from foundry TSMC. The chiplet implments the company’s NuLink PHY technology in support…
RISCs ‘not-in-Space’ (with statement from the Pulp Platform)
RISCs ‘not-in-Space’ (with statement from the Pulp Platform)
News |
The 432-Core Risc-V based Occamy processor board is ready to launch – with updated link! The ETH in Zurich, together with the Alma Mater Studiorum Universita di Bologna presented the…
Fraunhofer picks Achronix eFPGAs for chiplet demonstrator
Fraunhofer picks Achronix eFPGAs for chiplet demonstrator
Business news |
Collaboration to create an eFPGA-enabled chiplet solution aimed at validating next-generation chip-to-chip interconnect technology.
Chinese chiplet architecture for data centres, automotive
Chinese chiplet architecture for data centres, automotive
Business news |
Blue Ocean Smart System in China has developed a scalable chiplet architecture for high performance computing, automotive and data centre applications. The chiplet architecture uses multiple processors from VeriSilicon in…
Winbond to support chiplet interface standardisation
Winbond to support chiplet interface standardisation
Business news |
The UCIe Consortium open industry standard defines interconnect between chiplets within a package, enabling an open ecosystem.
OCP and JEDEC look to standardize chiplet part descriptions
OCP and JEDEC look to standardize chiplet part descriptions
Technology News |
Partnership establish a framework for the creation of new global standards for novel device components such as chiplets in emerging markets.
Intel goes slow, casts doubt on Italian chiplet fab
Intel goes slow, casts doubt on Italian chiplet fab
Business news |
Intel’s CEO Pat Gelsinger has cast doubt on Italy as the location for a US$5 billion chiplet assembly plant, saying other locations are possible. Intel is also apparently slowing down…
Intel close to Italy chiplet assembly plant – report
Intel close to Italy chiplet assembly plant – report
Business news |
Intel is close to announcing a plant to assemble 25 and 3D packages in Italy, according to a report from Reuters. The investment could be as much as $5bn although…
Open source chiplet interconnect spec aims for composable silicon
Open source chiplet interconnect spec aims for composable silicon
Market news |
The nonprofit Open Compute Project Foundation (OCP) has announced an open source chiplet interconnection specification optimized for maximum applicability enabling low cost and energy efficient implementations.
Ayar Labs raises $130m for optical chiplets
Ayar Labs raises $130m for optical chiplets
Business news |
Optical chiplet developer Ayar Labs has raised $130m from a consortium including Nvidia and Hewlett Packard Enterprises. The Series C round brings the total investment to $195m and was led…
Intel drives foundry business with $1bn fund
Intel drives foundry business with $1bn fund
Business news |
Intel has launched a $1bn fund to boost its fledgling foundry business by providing support to startups and IP providers. The Intel Foundry Service (IFS) has already joined RISC-V International…


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