MENU

ECO solution delivers fastest path to chip design closure

New Products |
By Rich Pell


Electronic design automation company Synopsys has announced what it claims is the breakthrough golden signoff engineering change order (ECO) solution that addresses lengthy engineering design closure times. The Synopsys PrimeClosure solution combines the company’s ECO signoff solutions, Synopsys PrimeECO and Synopsys Tweaker ECO, with “breakthrough” innovations, delivering the fastest ECO closure times with high capacity and golden Synopsys PrimeTime signoff accuracy.

Early customers, says the company, have achieved up to 45% better timing, up to 10% better power, up to 50% fewer ECO iterations and up to 10x higher design productivity compared to traditional ECO flows.

“Scaling productivity in hyperconvergent designs requires innovative solutions that can quickly and efficiently optimize power, performance and area (PPA) targets in very large design spaces,” says Jacob Avidan, senior vice president of Engineering for the Silicon Realization Group at Synopsys. “The Synopsys PrimeClosure product provides the industry with a breakthrough golden signoff ECO solution that enables designers to confidently achieve the fastest path to design closure, so companies can do more in significantly less time.”

Application areas like data centers, mobile, automotive, AI and IoT are demanding aggressive PPA targets. Advanced process nodes bring new physical rules and introduce new effects which impact PPA. The enormous size and complexity of deep-submicron designs means that every analysis and ECO optimization run to fix issues takes longer and consumes more compute resources. Handling this large number of violations and driving convergence to reduce it to zero is a big part of the ECO challenge, says the company.

The Synopsys PrimeClosure solution, with its surgical optimization feature, is designed to improve design metrics like PPA, timing, clock network, voltage drop, variation and aging. The solution is tightly integrated with Synopsys Fusion Compiler RTL-to-GDSII solution and Synopsys PrimeTime static timing analysis solution for golden signoff accuracy, delivering a full flow that accelerates design convergence and time-to-market of large designs.

With its gigachip hierarchical technology, the Synopsys PrimeClosure solution seamlessly scales designs with billion+ instances and hundreds of scenarios with a relatively small number of machines to deliver what is claimed to be the industry’s fastest turnaround time (TAT). Its optimized pruning technology efficiently sifts through thousands of scenarios and hundreds of hierarchical blocks to reduce the number of datasets for optimization, resulting in TAT speedup by over 40% and reduced memory by up to 60%.

Last-mile design optimization is critical to achieve optimal PPA. The Synopsys PrimeClosure solution has direct access to incrementally enabled placement, routing, extraction, physical verification, equivalence checking and signoff technologies from the Synopsys Digital Design Family.

The Synopsys PrimeClosure solution is integrated with Ansys RedHawk-SC digital power integrity signoff solution, enabling an automated late-stage golden signoff timing-aware ECO solution to accurately account for and fix up to 50% of late-stage dynamic voltage drop violations and maximize energy efficiency without impacting chip timing. The single-environment design closure cockpit ensures every change is fully implemented and validated and creates new opportunities for placement, routing, and timing co-optimization to achieve PPA results previously impossible in traditional design closure flows.

The Synopsys PrimeClosure solution is available to early adopters now with general availability targeted for December 2022.

Synopsys


Share:

Linked Articles
Smart2.0
10s