Analysis boost for sequential X-verification
Avery Design Systems has launched a major new release of its patented SimXACT analysis and chip verification tool.
The latest version adds features for sequential false X analysis and automatic repair and improved analysis and debug of clock gating logic. The new release also improves overall runtime performance.
SimXACT automates the tedious process of analyzing X propagations in gate-level simulations due to RTL vs. gate-level mismatches. These issues typically arise from gate-level simulator X-pessimism handling in glue logic and gated clocking and overly pessimistic library cell modelling.
This is one of the reasons Siemens EDA is aiming to buy the company.
SimXACT’s hybrid formal analysis runs during normal logic simulation, proving and fixing on-the-fly any false X’s arising from the simulated X pessimism present on flops, latches, memory inputs, and output pads.
The SimXACT-SA analyzes X propagations through multi-level sequential re-convergent logic and resolves false X’s so they do not propagate and cause gate-level simulation mismatch compared to RTL simulation.
Sequential analysis used to be only suited to conventional formal property checking solutions. Now SimXACT-SA’s hybrid formal analysis enables the use of simulation case-driven stimulus for more precise handling of sequential X propagation scenarios.
New patented technology identifies and fixes false Xs created by nested clock gates where conflicting clock gate enable conditions can create false Xs on the downstream FFs. A new GLS clock debug tool also compares islands of FFs controlled by the same clock gates between 0-delay and SDF-annotated simulations to help root cause hard-to-debug test failures.
Avery has also added heuristics for the SimXACT formal engine that better predicts functional impact of false Xs, resulting in smaller numbers of generated fixes while maintaining effectiveness for resolving false Xs that are functionally relevant.
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