Algorithm paves path to better video

Algorithm paves path to better video

Technology News |
The parallel algorithm described in a paper at the International Solid State Circuits Conference could become part of High Efficiency Video Coding (HVEC), the follow on to today’s H.264/AVC standard. The work promises significant improvements in the quality and power consumption for tomorrow’s systems that create or play video on…
By admin

Share:

The parallel algorithm described in a paper at the International Solid State Circuits Conference could become part of High Efficiency Video Coding (HVEC), the follow on to today’s H.264/AVC standard. The work promises significant improvements in the quality and power consumption for tomorrow’s systems that create or play video on anything from 3-D TVs to mobile handsets.

The HEVC effort aims to deliver by January 2013 a successor to today’s mainstream H.264/AVC standard. It targets a 50 percent improvement in coding efficiency, enabling Quad Full HD video resolutions of up to 4,096 x 2,160 pixels.

"There are test models people are building on and modifying now," Vivienne Sze, a member of technical staff at Texas Instruments told EE Times, suggesting the standard already is more than half done.

As many as 250 people have been attending the quarterly HEVC meetings, making hundreds of contributions so far. Sze presented her work on one of those HVEC contributions, a parallel-programming algorithm created as part of a doctoral thesis at MIT.

Sze defined a new and highly parallel version of the existing Context-based Adaptive Binary Arithmetic Coding scheme used in today’s H.264/AVC codecs. She called CABAC "a well known bottleneck [due to its] tight feedback loops."

The new technique creates a CABAC data structure which breaks up a video frame into several parts called interleaved entropy slices that can be processed in parallel. It further breaks those slices into several elements such as motion vectors and coefficients which also can be processed in parallel.

The ISSCC paper mapped the parallel CABAC algorithm onto a novel chip with 16 separate slice processors and 80 arithmetic decoders working in parallel. The technique could be used on any multicore architecture, Sze said.

The paper claimed the algorithm and chip could deliver six- to ten-fold increases in performance over published CABAC architectures. Specifically, the test chip decoded a 300 Mbit/second H.264/AVC stream at 1V, achieving a 2.3 Gbit/s bit rate. That’s fast enough to support the Quad Full HD resolution at 186 frames/s or at 24 frames/s when generating 7.8 views using Multiview Video Coding for stereoscopic 3-D video.

The massively parallel CABAC algorithm has been adopted into the so-called JM-KTA working code of the HEVC group. A decision whether to make it a part of the standard is still pending.

Linked Articles
eeNews Europe
10s