5G infrastructure needs programmability

5G infrastructure needs programmability

Technology News |
Alok Sanghavi surveys the 5G infrastructure landscape and makes the case for FPGAs and chiplet packaging to support evolving standards and high performance computation.
By Rich Pell

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Today there are 7.5 billion active mobile devices, that’s more devices than people. The impact that cellular connectivity is having on those who were previously digitally disenfranchised is profound; for example, just two years ago research showed that sub-Saharan Africa typically had 1 landline per 100 people, but 74 mobile connections.

There is no doubt that as wireless infrastructure progresses to 5G, it will become more pervasive and fully integrated with every aspect of our everyday lives. It will support our endless bandwidth demands and extend to more devices and usage models.

Trends
The key trends which must be accommodated by hardware designers include firstly, increased bandwidth for Enhanced Mobile Broadband (eMBB) and other applications, specifically driving the instantaneous available bandwidth at 10x current rates. Furthermore, deployment of 5G will also be staged depending on frequency band, sub-6GHz will be deployed first, followed by the contiguous bands at mmWave frequencies enabling more key eMBB applications at a later stage.

Secondly connectivity to many, many more devices will happen because of the Internet of Things (IoT). Expectations are that there will be 50 billion cellular connected devices within two years. This is partly addressed by existing standards but will also be encompassed by the current specification of Massive Machine Type Communications (mMTC) in Release 16 of 3GPP.

Third, we come to proliferation of new usage models, exerting new requirements onto mobile devices and the cellular infrastructure that they connect to. Good examples include low bandwidth, low power requirements for connecting battery-powered IoT end-points for connectivity and monitoring encompassed within mMTC.

High reliability, low latency cellular for vehicle-to-vehicle and vehicle-to-infrastructure connectivity (C-V2X) to complement existing V2X solutions like collision detection. Then high-reliability, low latency support for new and emerging applications like remote surgery and augmented/virtual-reality. The second two examples will be addressed by the upcoming 3GPP standard for Ultra-Reliable, Low Latency Connectivity (URLLC).

Wrapping up the trends is an important emerging need for Edge Analytics and Mobile Edge Compute. Gravity has rapidly shifted from previous assumptions of data moving to centralized compute resource for processing, to a new paradigm of a distributed computing resource located nearer the data’s origin. The reasons for this shift include strict latency requirements, an appreciation that the sheer volume of data can be overwhelming and the desire to optimize networking resource and energy.


Layer 1 processing
The baseband takes the data from the network interface (e.g., Ethernet) and transforms it to/from complex samples that are transmitted over the fronthaul interface to the radio.

The unique requirements of 5G can be successfully addressed by a SoC architecture comprising a high-performance CPU subsystem and hardware processing elements, including FPGA re-programmable acceleration. Here layer 1 of the baseband processing can be mapped onto the key processing elements such as the processor subsystem, CPU and DSP cores, and fixed and flexible hardware acceleration as shown in Figure 1.

Figure 1: Key baseband processing elements (click on diagram to enlarge image).

Flexibility in the front-haul
In addition to the processing elements previously described, there is a flexible antenna interface block; this is the element required to connect from the baseband to the Radio Unit. Traditionally, this was Common Public Radio Interface (CPRI), or sometimes Open Base Station Architecture Initiative (OBSAI). Increasingly, there is a move to specify a more flexible fronthaul interface, to allow a different mapping between baseband and Radio (as shown in Figure 1).

IEEE has an ongoing activity on Next Generation Fronthaul Interface NGFI (IEEE1914), comprising of the IEEE1914.1 standard for Packet-based Fronthaul Transport Networks and IEEE1914.3 Radio over Ethernet (RoE) Encapsulations and Mappings. In parallel, there are other industry initiatives that specify a 5G fronthaul interface and share similar aspects, for example eCPRI.

Due to the variety of different specifications, standards and requirements for the fronthaul interface, FPGAs are typically used to support this interface, as shown in Figure 1 above.


Discrete architecture cuts time-to-market
The next illustration (Figure 2 below) maps the required processing elements for 5G onto a discrete implementation with separate devices for CPU SoC, look-aside FPGA acceleration and antenna interfacing. This configuration reflects implementation that could deploy in 5G prototyping and early-production, before optimized 5G ASICs are available.

CPU system-on-chip includes, for example, an ARM processing complex as well as DSP cores for Layer-1 processing and hardened accelerators, for fixed, well-defined functionality. In this example, it is assumed that an existing 4G ASIC SoC is available and therefore has general purpose acceleration (e.g. MACSEC) as well as LTE specific acceleration: Forward Error Correction (specifically turbo codec), Fast Fourier Transform, and Discrete Fourier Transform to support SC-FDMA on the uplink.

Flexible Antenna Interface – As described earlier, the fronthaul antenna interface is well suited to an FPGA implementation. This is configured in-line, with the data flowing from the Radio Unit (on the uplink) and then the protocol being converted to something with standard connectivity like Ethernet.

Hardware Acceleration FPGA – A look-aside acceleration FPGA implements all necessary computationally-intensive functions that are unavailable on the base SoC. This can be 5G specific functions or those previously not envisioned.

In the example shown here, a CCIX interconnect is used. The standard allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to a number of acceleration devices including FPGAs and custom ASICs.

Figure 2: Discrete archtecture for 5G time-to-market solution (click on diagram to enlarge image).

The Chiplet Alternative
Figure 3 shows a comparable architecture as that shown in Figure 2 but reconfigured with a chiplet based approach. In this case, a higher bandwidth, lower latency and lower power interface is used to connect the CPU SoC die with a look-aside hardware acceleration FPGA chiplet. The FPGA device supporting the fronthaul connection to the Radio Unit is not package integrated in this example but could be; indeed, it could be the same device chiplet as the hardware acceleration chiplet, if there are sufficient resources.

Figure 3: Chiplet-based approach for greater integration (click on diagram to enlarge image).

The two primary techniques for package integration are with a silicon interposer or with an organic substrate and some form of Ultra-Short Reach (USR) transceiver.

A fully integrated 5G vision
Finally, Figure 4 shows the final, most integrated, architecture for baseband considered here. This approach includes the same processing elements as previously, with the same functionality, but with embedded FPGA monolithically integrated on the die.

Figure 4: Heterogeneous multi-core system-on-chip with monolithic integration applied to 5G baseband (click on diagram to enlarge image).

This tightly integrated approach of monolithic integration has a number of benefits. This interface has higher bandwidth, lower latency and lower energy-per-bit than that observed in a chiplet based approach. Moreover, the resource mix can be tailored to the specific application under consideration and therefore unwanted interfaces, memory and core logic is avoided. This also results in the lowest unit cost of the three architectures under consideration.


As described previously, the primary objective here is to afford improved time-to-market, flexibility and future proofing. Time-to-market comes from the fact that the SoC can be taped-out earlier, as late changing modifications (e.g. the emergence of Polar Codes in 5G) can be targeted into eFPGA rather than ASIC.

Flexibility results from new or unexpected algorithms (e.g. new encryption standards) can be addressed in embedded programmable logic rather than software or external FPGA. Finally, future proofing enables the SoC lifecycle to be extended, as the large emerging requirements, for example for new standards such as URLLC and mMTC, can be addressed by the existing product rather than requiring a new development.

In brief conclusion from the 5G perspective, a highly programmable solution enables a faster time to market. It is no longer necessary to delay a system-on-chip tape-out until standards are finalized; late changing requirements can be absorbed in software or programmable hardware. This is a powerful advantage with the relentless (and increasing) pressure for early 5G deployments, coupled with the relentless emergence of new standards.

Alok Sanghavi is a senior manager of product marketing at Achronix Semiconductor Corporation. Prior to joining Achronix, Sanghavi was at Toshiba, where he led the product definition of several semiconductor chipsets into the market. He holds an MBA from the University of California at Davis and Master of Science degree in Electrical Engineering from New York University.

www.achronix.com

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