Safety and Power Architectures that Enable Autonomous Driving Embedded Systems

April 26, 2017 // By David Lopez, Maxime Clairet, NXP Semiconductors
Safety and Power Architectures that Enable Autonomous Driving Embedded Systems
The electrification of the car and the transformation to autonomous driving will lower emissions, reduce traffic congestion and other hazards. This will be made possible by Advanced Drivers Assistance Systems (ADAS) that act on safety applications to control steering, braking and transmission without taking inappropriate actions.

To manage the risk of operations, the development of these systems follows the highest ISO 26262 [1] Automotive Safety Integrity Level (ASIL D) to guarantee a safe state activation when a safety goal is violated.

All safety electronic systems require a safety microcontroller and a reliable, safe source of power management connected to the car battery: this is the System Basis Chip (SBC). Safety microcontrollers and safety system basis chips are the backbone of embedded system architectures that includes independent hardware monitoring.

This article highlights the latest functional safety innovations at the power management level (SBC), from the development phase to system design, and underscores the link to reliability and how to enable hardware that is safety ready. It will also demonstrate how an architecture developed for ASIL D can help improve the functional robustness of an embedded system with a destructive test performed on the Integrated Circuit (IC).

Introduction to ISO 26262 functional safety standard

Functional safety means the absence of unreasonable risk due to hazards caused by the malfunction of systems. To significantly reduce the risk of malfunction, it is critical to understand and assess the 2 types of failures that can occur.

1- Systematic failures can only be eliminated by a change in the design of the manufacturing process, operational procedures, documentation or other relevant factors. The probability of a systematic failure occurring is reduced through a robust development process and quality management.

2- Random failures, which occur unpredictably during the lifetime of a hardware element, follow a probability distribution. Those failures could result from a permanent or transient occurrence of a perturbed environment, or from the intrinsic technology’s performance across the system’s lifetime. Risk reduction linked to the random failure is covered by dedicated system architectures and/or IC detection strategy. This is one of SBC’s purposes.

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