Power Limit for Insulation Capabilities of Modern IGBT/MOSFET Gate Drivers

February 20, 2019 //By Bernhard Strzalkowski, Analog Devices
Power Limit for Insulation Capabilities of Modern IGBT/MOSFET Gate Drivers
This article investigates a gate driver’s isolation withstand performance through the intentional destruction of IGBT/MOSFET power switches.

In high reliability, high performance applications, like electrical/hybrid vehicles, isolated gate drivers need to ensure the isolation barrier stays intact under all circumstances. The power density of modern power converters/inverters is rising due to the continuous improvement of Si-MOSFET/IGBT and the introduction of GaN and SiC technologies. Therefore, new, highly integrated, isolated, and robust gate drivers are needed. Those drivers provide a small form factor because the electrical isolation is already integrated on the driver chip. This electrical isolation can be performed by means of integrated high voltage microtransformers or capacitors.1, 2, 3 One unpredictable system fault can cause damage to, and the explosion of, power switches or even of the whole power inverter. Therefore, gate driver isolation safety performance needs to be investigated for high power density inverters. The isolation reliability must be tested and validated, in the worst case, when power-switches destruct.

Introduction

An inverter’s bank capacitor of several thousand µF will be rapidly discharged in the worst case, when the high power MOSFET/IGBT fails. The released energy causes MOSFET/IGBT damage, package explosion, and plasma exit into the environment.4 One part of the energy flows into the gate-driver circuit causing electrical overstress.5 Due to extremely high power density, the driver chip should be constructed to maintain electrical isolation even if the chip itself fails.

Construction of Modern, Highly Integrated Gate Drivers

Chip-scale isolation adapts the planar microtransformer approach to provide electrical isolation. It is fabricated using wafer-level techniques and configured in a semiconductor component form-factor.1 An iCoupler® channel consists of two integrated circuits (ICs) combined with chip-scale transformers (Figure 1). An insulation layer provides the isolation barrier to separate the top and bottom coils of each transformer (Figure 2). Digital isolators use a minimum of 20 μm thick polyimide insulating layers between planer transformer coils that are part of the wafer fabrication process. This manufacturing process allows for the isolation elements to be integrated with any foundry semiconductor process at low cost and with excellent quality and reliability. The cross section in Figure 2 shows the turns of the top and bottom coils separated by the thick polyimide layer.


Figure 1. Chip arrangement of MOSFET half-bridge driver ADuM3223.

A split lead-frame within the package completes the isolation. When a gate driver output chip is damaged due to a power switch explosion, the internal chip partitioning and arrangement must ensure the isolation layer remains intact. Several protection measures have been implemented to ensure gate driver isolation survival:

  • Properly dimensioning the external circuit to limit energy flow into the gate driver chip
  • Appropriate placement of output transistors on the driver chip
  • Appropriate placement of microtransformer on the chip
  •  Appropriate arrangement control and driver chip inside of the package
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