Discrete architecture cuts time-to-market
The next illustration (Figure 2 below) maps the required processing elements for 5G onto a discrete implementation with separate devices for CPU SoC, look-aside FPGA acceleration and antenna interfacing. This configuration reflects implementation that could deploy in 5G prototyping and early-production, before optimized 5G ASICs are available.
CPU system-on-chip includes, for example, an ARM processing complex as well as DSP cores for Layer-1 processing and hardened accelerators, for fixed, well-defined functionality. In this example, it is assumed that an existing 4G ASIC SoC is available and therefore has general purpose acceleration (e.g. MACSEC) as well as LTE specific acceleration: Forward Error Correction (specifically turbo codec), Fast Fourier Transform, and Discrete Fourier Transform to support SC-FDMA on the uplink.
Flexible Antenna Interface - As described earlier, the fronthaul antenna interface is well suited to an FPGA implementation. This is configured in-line, with the data flowing from the Radio Unit (on the uplink) and then the protocol being converted to something with standard connectivity like Ethernet.
Hardware Acceleration FPGA - A look-aside acceleration FPGA implements all necessary computationally-intensive functions that are unavailable on the base SoC. This can be 5G specific functions or those previously not envisioned.
In the example shown here, a CCIX interconnect is used. The standard allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to a number of acceleration devices including FPGAs and custom ASICs.