5G infrastructure needs programmability: Page 2 of 5

February 15, 2019 //By Alok Sanghavi, Achronix Semiconductor Corporation
5G infrastructure needs programmability
Alok Sanghavi surveys the 5G infrastructure landscape and makes the case for FPGAs and chiplet packaging to support evolving standards and high performance computation.

Layer 1 processing
The baseband takes the data from the network interface (e.g., Ethernet) and transforms it to/from complex samples that are transmitted over the fronthaul interface to the radio.

The unique requirements of 5G can be successfully addressed by a SoC architecture comprising a high-performance CPU subsystem and hardware processing elements, including FPGA re-programmable acceleration. Here layer 1 of the baseband processing can be mapped onto the key processing elements such as the processor subsystem, CPU and DSP cores, and fixed and flexible hardware acceleration as shown in Figure 1.

Figure 1: Key baseband processing elements (click on diagram to enlarge image).

Flexibility in the front-haul
In addition to the processing elements previously described, there is a flexible antenna interface block; this is the element required to connect from the baseband to the Radio Unit. Traditionally, this was Common Public Radio Interface (CPRI), or sometimes Open Base Station Architecture Initiative (OBSAI). Increasingly, there is a move to specify a more flexible fronthaul interface, to allow a different mapping between baseband and Radio (as shown in Figure 1).

IEEE has an ongoing activity on Next Generation Fronthaul Interface NGFI (IEEE1914), comprising of the IEEE1914.1 standard for Packet-based Fronthaul Transport Networks and IEEE1914.3 Radio over Ethernet (RoE) Encapsulations and Mappings. In parallel, there are other industry initiatives that specify a 5G fronthaul interface and share similar aspects, for example eCPRI.

Due to the variety of different specifications, standards and requirements for the fronthaul interface, FPGAs are typically used to support this interface, as shown in Figure 1 above.

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