RISC-V SoC FPGA architecture brings real-time to Linux

December 06, 2018 // By Rich Pell
Microchip Technology (Chandler, AZ), via its Microsemi Corporation subsidiary (Aliso Viejo, CA), has unveiled the architecture for a new class of SoC FPGAs that it says combines the industry's lowest power mid-range PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA).

The new PolarFire SoC architecture brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. While traditional system-on-chip (SoC) field programmable gate arrays (FPGAs) blending reconfigurable hardware with Linux-capable processing on a single chip provide developers ideal devices for customization, says the company, they consume too much power, lack proven levels of security and reliability, or use inflexible and expensive processing architectures.

Developed in collaboration with SiFive, the new PolarFire SoC architecture features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad, or a direct access memory, allowing designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal and space constrained applications in collaborative, networked IoT systems.

"The PolarFire SoC architecture is a compelling combination of low power, security, and reliability in a configurable device that brings real-time to Linux," says Bruce Weyer, vice president of the Programmable Solutions business unit at Microchip. "Coupled with our robust Mi-V RISC-V ecosystem and Microchip's extensive portfolio of system solutions, the PolarFire SoC architecture gives customers an excellent platform to meet computing's next great challenges."

PolarFire SoC includes extensive debug capabilities including instruction trace, 50 breakpoints, passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors, and FPGA fabric monitors, as well as the company's built-in two-channel logic analyzer SmartDebug. The architecture includes reliability and security features such as single error correction and double error detection (SEC-DED) on all memories, physical memory protection, a differential power analysis (DPA) safe crypto core, defense-grade secure boot, and 128Kb flash boot memory.

SiFive CEO Naveed Sherwami says, "As a fully customizable, programmable RISC-V platform, the PolarFire SoC architecture gives designers the freedom to create innovative Linux-based SoCs in novel and interesting ways tailored for their distinct, domain-specific requirements. By leveraging SiFive's market-leading U54-MC CPU core complex, PolarFire SoC will enable designers to overcome


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