Processor model generator is AI driven

October 05, 2018 // By Rich Pell
System simulation software company Mirabilis Design (Sunnyvale, CA) has unveiled an artificial intelligence (AI)-driven process generator for performance analysis and architecture exploration of system-on-chip (SoC) and embedded systems.

The VisualSim AI Processor Generator is an add-on to the company's VisualSim Architect 18.3 modeling and simulation platform, which, says the company, is used extensively in designing products from aircraft avionics to adventure cameras, and processors to safety critical systems. It generates a model that is pipeline-accurate and has port integration with standard buses and memories, and which is used to compare different processor families, optimize the specification, and identify system bottlenecks.

The AI Processor Generator currently supports the entire ARM and PowerPC processor families. Additional support is planned for DSP and x86 architectures.

"Selecting the right processor, configuring multi-cores, and establishing the right topology is very challenging for the new breed of systems," says Deepak Shankar, Founder of Mirabilis Design. "Acquiring boards and loading software on each processor instance is expensive; emulators, RTL and cycle-accurate models take a long time to simulate and are not easily available; virtual prototypes do not provide timing accuracy; while analytical models cannot handle the complex traffic patterns. AI technology has evolved and enabled us to take a spreadsheet input and generate a processor model that is fast, accurate and visual."

The company used AI to identify patterns in over 100 processors. Using these patterns, VisualSim AI Processor Generator has created a unique input spreadsheet. Using this input and the learning algorithm database loaded into the generator, existing and future processors models are generated.

Data for the input spreadsheet is available in the vendor datasheet. The generated model supports variable processor pipelines, SIMD/MIMD, multi-thread, multi-level cache hierarchy, coherency, heterogeneous execution units, buffers, and bus interfaces.

The generated model has over 150 statistics for cache hit-ratio, stalls and utilization. The processor has probes to trace pipeline execution sequence, prefetch requests, interrupts and preemption.

Commercial shipment of the AI processor generator is planned for late October. The generator will be available for viewing and experimenting at ARM Techcon on October 17-18, 2018 in San Jose, CA.

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