The move was expected (see High-flying Achronix plans move to ML).
Achronix Speedcore7t delivers a 60 percent faster performance, 50 percent lower power and 65 percent smaller die size compared with the existing product line, Speedcore22i, said Robert Blake, CEO of Achronix. And just as FPGA vendors have made memory blocks and DSPs available as special blocks for inclusion in FPGAs, Achronix has prepared machine learning processor blocks that are rich in multiply and matrix-multiply resources to accelerate AI/ML applications.
The Speedcore7t has a couple of changes to its basic fabric. The company has moved to a six-input lookup table (6-LUT) compared to the 4-LUT in the Speedcore22. In addition there are features such as 8:1 multiplexers, 8-bit ALUs and 8-bit bus maximum functions much used in AI/ML, double registers per LUT and dedicated shift registers.
The move has increased the functional efficiency of the FPGA fabric, Achronix said. Leading FPGAs implement 6 by 6 multipliers in 21 LUTs whereas Speedcore Gen4 implements 6 by 6 multipliers in 11 LUTs and can operate at 1 GHz.
The Speedcore7t also includes a second hierarchy of high performance routing. Separating bus routing from the standard nearest neighbour routing prevents congestion and allows islands of compute to communicate quickly to distant regions on the die and is particularly suited to running between memories the machine learning processors. It can be selected to originate and land at any LUT and is effectively a run-time configurable switching network.
This is the first time that run-time logic functionality is available in the routing structure and it provides a solution for high-bandwidth and low-latency applications.
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